Technical Field
Embodiments described herein relate to data communication and more particularly, to performing training of bit-serial data links.
Description of the Related Art
The data throughput of integrated circuits continues to increase as applications' demand and consumption of data increases. For example, the rate of improvement in microprocessor speed continues to exceed the rate of improvement in memory speed. Increasing the rate at which data is transmitted increases the timing requirements of the circuitry used to transmit and receive the data. In many circuits utilized in computing devices and computing systems, data is transferred within these circuits using a global clock. For example, the rising edge of the clock may load the data coming in to a flip-flop, and then the data can be passed on or processed from the flip-flop. In some scenarios, a single clock may be used to latch in a data bus of multiple data lanes. However, this limits the speed of the data bus because the transition of the clock has to be used for the whole data bus, but some bits of data may take longer to get down the bus relative to other bits of data. If the variation between data lanes is too high, then a location for placing the clock edge to correctly clock in the whole data bus may not exist.